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Flash Memory Plus SRAM -- Reduces Memory Board Space Required, Simplifying PCB Design Complexity SCSP Technology -- Smallest Memory Subsystem Footprint -- Area : 8 x 10 mm for 16 Mbit (0.13 m) Flash + 2 Mbit or 4 Mbit SRAM -- Area : 8 x 12 mm for 32 Mbit (0.13 m) Flash + 4 Mbit or 8 Mbit SRAM -- Height : 1.20 mm for 16 Mbit (0.13 m) Flash + 2 Mbit or 4 Mbit SRAM, and 32 Mbit (0.13um) Flash + 8 Mbit SRAM -- Height : 1.40 mm for 32 Mbit (0.13 m) Flash + 4 Mbit SRAM -- This Family also includes 0.25 m, 0.18 m, and 0.13 m technologies Advanced SRAM Technology -- 70 ns Access Time -- Low Power Operation -- Low Voltage Data Retention Mode Intel(R) Flash Data Integrator (FDI) Software -- Real-Time Data Storage and Code Execution in the Same Memory Device -- Full Flash File Manager Capability

Advanced+ Boot Block Flash Memory --70 ns Access Time --Instant, Individual Block Locking --128 bit Protection Register --12 V Production Programming --Fast Program and Erase Suspend --Extended Temperature -25 C to +85 C Blocking Architecture --Block Sizes for Code + Data Storage --4-Kword Parameter Blocks --64-Kbyte Main Blocks --100,000 Erase Cycles per Block Low Power Operation --Asynchronous Read Current: 9 mA (Flash) --Standby Current: 7 A (Flash) --Automatic Power Saving Mode Flash Technologies --0.25 m ETOXTM VI, 0.18 m ETOXTM VII and 0.13 m ETOXTM VIII Flash Technologies
The Intel(R) Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device incorporates flash memory and static RAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The C3 SCSP memory device offers a protection register and flexible block locking to enable next generation security capability. Combined with the Intel(R) Flash Data Integrator (Intel(R) FDI) software, the C3 SCSP memory device provides a cost-effective, flexible, code plus data storage solution.
Order Number: 252636, Revision: 004 26 Aug 2005
om .c 4U et he aS at .D w w w
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL (R) PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) Advanced+ Boot Block Flash Memory (C3) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel, the Intel logo, Intel StrataFlash, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. All rights reserved.
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Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
Datasheet
C3 SCSP Flash Memory
Contents
1.0 Introduction....................................................................................................................................6 1.1 1.2 1.3 1.4 2.0 Document Conventions ........................................................................................................ 6 Product Overview .................................................................................................................6 Package Ballout .................................................................................................................... 8 Signal Definitions .................................................................................................................. 9
Principles of Operation ...............................................................................................................11 2.1 Bus Operation ..................................................................................................................... 11 2.1.1 Read ......................................................................................................................12 2.1.2 Output Disable ....................................................................................................... 12 2.1.3 Standby.................................................................................................................. 13 2.1.4 Flash Reset............................................................................................................ 13 2.1.5 Write ......................................................................................................................13
3.0
Flash Memory Modes of Operation............................................................................................14 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Read Array (FFh) ................................................................................................................ 14 Read Identifier (90h) ........................................................................................................... 14 Read Status Register (70h) ................................................................................................ 15 3.3.1 Clear Status Register (50h) ................................................................................... 16 CFI Query (98h) .................................................................................................................. 16 Word Program (40h/10h) .................................................................................................... 16 3.5.1 Suspending and Resuming Program (B0h/D0h)....................................................17 Block Erase (20h) ...............................................................................................................18 3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................................ 18 Block Locking......................................................................................................................20 3.7.1 Block Locking Operation Summary........................................................................ 21 3.7.2 Locked State .......................................................................................................... 21 3.7.3 Unlocked State ...................................................................................................... 21 3.7.4 Lock-Down State ................................................................................................... 21 3.7.5 Reading Lock Status for a Block............................................................................ 22 3.7.6 Locking Operation During Erase Suspend ............................................................ 22 3.7.7 Status Register Error Checking ............................................................................. 22 128 Bit Protection Register .................................................................................................23 3.8.1 Reading the Protection Register ............................................................................ 23 3.8.2 Programming the Protection Register (C0h).......................................................... 24 3.8.3 Locking the Protection Register ............................................................................. 24
3.8
4.0
Power and Reset Considerations .............................................................................................. 25 4.1 4.2 Power-Up/Down Characteristics ......................................................................................... 25 Additional Flash Features ................................................................................................... 25 4.2.1 Improved 12 Volt Production Programming ...........................................................25 4.2.2 F-VPP VPPLK for Complete Protection .............................................................. 25
5.0
Electrical Specifications ............................................................................................................. 26 5.1 5.2 5.3 Absolute Maximum Ratings ................................................................................................ 26 Operating Conditions .......................................................................................................... 27 Capacitance ........................................................................................................................ 27
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6.0 7.0
DC Characteristics.............................................................................................................. 28 Flash AC Characteristics. ................................................................................................... 32 Flash AC Characteristics--Write Operations...................................................................... 33 Flash Erase and Program Timings(1)................................................................................. 34 Flash Reset Operations ...................................................................................................... 36 SRAM AC Characteristics--Read Operations.................................................................... 37 SRAM AC Characteristics--Write Operations .................................................................... 38 SRAM Data Retention Characteristics--Extended Temperature ....................................... 40
Migration Guide Information ...................................................................................................... 41 System Design Considerations.................................................................................................. 41 7.1 Background......................................................................................................................... 41 7.1.1 Flash + SRAM Footprint Integration ...................................................................... 41 7.1.2 C3 Flash Memory Features ................................................................................... 42 Flash Control Considerations ............................................................................................. 42 7.2.1 F-RP# Connected to System Reset....................................................................... 42 7.2.2 F-VCC, F-VPP and F-RP# Transition .................................................................... 42 Noise Reduction ................................................................................................................. 43 Simultaneous Operation ..................................................................................................... 44 7.4.1 SRAM Operation during Flash "Busy" ................................................................... 45 7.4.2 Simultaneous Bus Operations ............................................................................... 45 Printed Circuit Board Notes ................................................................................................ 45 System Design Notes Summary......................................................................................... 45
7.2
7.3 7.4
7.5 7.6 A B
Program/Erase Flowcharts ............................................................................................................ 46 CFI Query Structure ...................................................................................................................... 52 B.1 B.2 B.3 B.4 B.5 B.6 B.7 Query Structure Output....................................................................................................... 52 Query Structure Overview .................................................................................................. 53 Block Lock Status Register................................................................................................. 54 CFI Query Identification String............................................................................................ 54 System Interface Information.............................................................................................. 55 Device Geometry Definition ................................................................................................ 56 Intel-Specific Extended Query Table .................................................................................. 57
C D E F
Word-Wide Memory Map Diagrams .............................................................................................. 59 Device ID Table ............................................................................................................................. 66 Protection Register Addressing ..................................................................................................... 67 Mechanical and Shipping Media Details........................................................................................ 68 F.8 F.9 Mechanical Specification .................................................................................................... 68 Media Information ............................................................................................................... 71
G H
Additional Information.................................................................................................................... 73 Ordering Information...................................................................................................................... 74
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Datasheet
C3 SCSP Flash Memory
Revision History
Date of Revision 02/11/03 01/29/04 03/05 26 Aug 2005 Version -001 -002 -003 -004 Description Initial release, Stacked Chip Scale Package Minor text edits. Updated Ordering Information figures and table in Appendix H. Updated Ordering Information to add PF28F1602C3TD70.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
1.0
Introduction
This document contains the specifications for the Intel(R) Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device. C3 SCSP memory solutions are offered in the following combinations:
* * * *
32-Mbit flash + 8-Mbit SRAM 32-Mbit flash + 4-Mbit SRAM 16-Mbit flash + 4-Mbit SRAM 16-Mbit flash memory + 2-Mbit SRAM
1.1
Document Conventions
Throughout this document, the following conventions have been adopted.
* Voltages:
-- 2.7 V refers to the full voltage range, 2.7 V-3.3V -- 12 V refers to 11.4 V to 12.6 V
* Main block(s): 32-Kword block * Parameter block(s): 4-Kword block
1.2
Product Overview
The C3 SCSP device combines flash memory and SRAM into a single package, which provides secure low-voltage memory solutions for portable applications. The flash memory provides the following features:
* Enhanced security. * Instant locking/unlocking of any flash block with zero-latency * A 128-bit protection register that enables unique device identification, to meet the needs of
next generation portable applications.
* Improved 12 V production programming for increased factory throughput.
Table 1. Block Organization (x16)
Memory Device 32-Mbit Flash 16-Mbit Flash 2-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM Note: All words are 16 bits each. Kwords 2048 1024 128 256 512
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Datasheet
C3 SCSP Flash Memory
The flash memory is asymmetrically-blocked to enable system integration of code and data storage in a single device. Each flash block can be erased independently of the others up to 100,000 times. The flash memory has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map, to accommodate different microprocessor protocols for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any individual flash memory block can be locked or unlocked instantly to provide complete protection for code or data (see Section 5.7, "Flash Erase and Program Timings(1)" on page 34 for details). The flash memory contains both a Command User Interface (CUI) and a Write State Machine (WSM).
* The CUI is the interface between the microcontroller and the internal operation of the flash
memory.
* The internal WSM automatically executes the algorithms and timings necessary for program
and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. To indicate the status of the WSM, the flash memory status register signifies block erase or word program completion and status. Flash program and erase automation enables executing program and erase operations using an industry-standard two-write command sequence to the CUI.
* Program operations are performed in word increments. * Erase operations erase all locations within a block simultaneously.
The system software can suspend both program and erase operations to read from any other flash block. In addition, data can be programmed to another flash block during an erase suspend. The C3 SCSP memory device offers two low-power savings features to significantly reduce power consumption:
* Automatic Power Savings (APS) for flash memory. The C3 SCSP memory device
automatically enters APS mode after a read cycle completes from the flash memory.
* Standby mode for flash and SRAM. This mode is initiated when the system deselects the
device by driving F-CE# and S-CS1# or S-CS2 inactive. To reset the flash memory, lower the F-RP# signal to GND. Setting F-RP# to GND provides CPU memory reset synchronization and additional protection against bus noise that can occur during system reset and power-up/power-down sequences.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
1.3
72-
Package Ballout
66-Ball SCSP Package Ballout
Figure 1.
1 A NC B
2
3 A20 A16
4 A11 A8
5 A15 A10 A21
6 A14 A9
7 A13
8
9
10
11
12 NC
A12 F-VSS F-VCCQ
DQ15 S-WE# DQ14 DQ7 DQ13 DQ6 DQ4 DQ5
C F-WE# NC D S-VSS F-RP# A22 E F-WP# F-VPP A19 F S-LB# S-UB# S-OE# G A18 H NC NC A5 A4 A0 F-CE# F-VSS F-OE# NC NC A17 A7 A6 A3 A2 A1 S-CS1# DQ9 DQ8 DQ0 DQ1 DQ11 DQ10 DQ2 DQ3 DQ12 S-CS2 S-VCC F-VCC
Top View, Balls Down
Notes: 1. Flash memory upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash memory and SRAM combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball location A10 is NC on 16/2 devices only. 2. To maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land pad directly to the land pad for the G4 (A17) ball.
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Datasheet
C3 SCSP Flash Memory
1.4
Signal Definitions
Table 2 defines the signals shown in Figure 1 "66-Ball SCSP Package Ballout" on page 8.
Table 2.
Symbol
Intel(R) Advanced+ Boot Block SCSP Ball Descriptions (Sheet 1 of 2)
Type Name and Function ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. * 2-Mbit : A[16:0]
A[20:0]
INPUT
* 4-Mbit : A[18:0] * 16-Mbit : A[19:0] * 32-Mbit A[20:0] DATA INPUTS/OUTPUTS: * Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle during a flash program command.
DQ[15:0]
INPUT / OUTPUT
* Inputs commands to the flash memory Command User Interface when F-CE# and F-WE# are asserted. * Data is internally latched. * Outputs array, configuration, and status register data. The data balls float to tristate when the chip is deselected or the outputs are disabled. FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders, and sense amplifiers.
F-CE#
INPUT
* F-CE# is active low. * F-CE# high deselects the flash memory device and reduces power consumption to standby levels. SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders, and sense amplifiers.
S-CS1#
INPUT
* S-CS1# is active low. * S-CS1# high deselects the SRAM memory device and reduces power consumption to standby levels. SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders, and sense amplifiers.
S-CS2
INPUT
* S-CS2 is active high. * S-CS2 low deselects the SRAM memory device and reduces power consumption to standby levels.
F-OE# S-OE#
INPUT INPUT
FLASH OUTPUT ENABLE: Enables flash memory outputs through the data buffers during a read operation. F-OE# is active low. SRAM OUTPUT ENABLE: Enables SRAM outputs through the data buffers during a read operation. S-OE# is active low. FLASH WRITE ENABLE: Controls writes to the flash memory command register and memory array. F-WE# is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse. SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low. SRAM UPPER BYTE ENABLE: Enables the upper byte for SRAM (DQ8-DQ15). S-UB# is active low. SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ 0-DQ7). S-LB# is active low.
F-WE# S-WE# S-UB# S-LB#
INPUT INPUT INPUT INPUT
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 2.
Symbol
Intel(R) Advanced+ Boot Block SCSP Ball Descriptions (Sheet 2 of 2)
Type Name and Function FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, V IH) to control reset/deep power-down mode.
F-RP#
INPUT
* When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). * When F-RP# is at logic high, the device is in standard operation. * When F-RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature. * When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. After F-WP# goes low, any blocks previously marked lock-down revert to that state. * When F-WP# is logic high, the lock-down mechanism is disabled. Blocks previously locked-down are now locked, and can be unlocked or locked through software. See Section 7.0, "System Design Considerations" on page 41 for details on block locking.
F-WP#
INPUT
F-VCC F-VCCQ S-VCC
SUPPLY SUPPLY SUPPLY
FLASH POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device core operations. FLASH I/O POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device I/O operations. SRAM POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device operations. See Section 7.2.2, "F-VCC, F-VPP and F-RP# Transition" on page 42 for details of power connections. FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.3 V or 11.4 V-12.6 V] Operates as an input at logic levels to control complete flash memory protection. Supplies power for accelerated flash memory program and erase operations in 12 V 5% range. This ball cannot be left floating. Lower F-VPP VPPLK, to protect all contents against Program and Erase commands. Set F-VPP = F-VCC for in-system read, program and erase operations. In this configuration, F-V PP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note: If F-VPP is driven by a logic signal, then V IH = 1.65 V. That is, F-VPP must remain above 1.65 V to modify in-system flash memory.
F-VPP
INPUT / SUPPLY
Raise F-VPP to 12 V 5% for faster program and erase in a production environment. 12 V 5% to F-VPP can be applied for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP can be connected to 12 V for a total of 80 hours maximum. F-VSS S-VSS NC SUPPLY SUPPLY FLASH GROUND: For all internal circuitry. All ground inputs must be connected. SRAM GROUND: For all internal circuitry. All ground inputs must be connected. NOT CONNECTED: Internally disconnected within the device.
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Datasheet
C3 SCSP Flash Memory
2.0
Principles of Operation
The flash memory uses a CUI and automated algorithms to simplify program and erase operations. To automate program and erase operations, the WSM handles data and address latches, WE#, and system status requests.
Figure 2.
Intel(R) Advanced+ Boot Block SCSP Block Diagram
F-VCC F-OE# F-CE# F-WP# F-RP#
Flash 28F160C3 or 28F320C3
F-VCCQ F-WE# F-VPP F-VSS
A[Max:0]
D[15:0]
S-VCC S-CS1 S-CS2 S-OE#
SRAM 2-, 4- or 8-Mbit
S-VSS S-WE# S-UB# S-LB#
.
2.1
Bus Operation
All bus cycles to or from the SCSP conform to standard microcontroller bus cycles. Four control signals dictate the data flow in and out of the flash component:
* * * * * * * *
F-CE# F-OE# F-WE# F-RP#
Four separate control signals handle the data flow in and out of the SRAM component: S-CS1# S-CS2 S-OE# S-WE#
Table 2 on page 9 and Table 3 on page 12 summarize these bus operations .
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
2.1.1
Read
The flash memory device provides four read modes:
* * * *
Read array Read identifier Read status CFI query
These flash memory read modes do not depend on the F-VPP voltage. Upon initial device power-up or after exit from reset, the flash memory device automatically defaults to read array mode. F-CE# and F-OE# must be asserted to obtain data from the flash memory device. The SRAM provides only one read mode. S-CS1#, S-CS2, and S-OE# must be asserted to obtain data from the SRAM device. See Table 3 for a summary of operations.
Table 3.
Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations
Flash Signals SRAM Signals Memory Output Memory Bus Control
S-WE#
F-WE#
F-RP#
F-CE#
S-CS2
Modes
S-UB#,S-LB#(1)
S-OE1#
F-OE1#
S-CS1#
D0 - D15
Notes
Read FLASH Write Standby Output Disable Reset Read
H H H H L
L L H L X
L H X H X
H SRAM must be in High Z L X H X L H H X L H L H X X H H L X X H L L X Any SRAM mode is allowable
Flash Flash Other Other Other SRAM SRAM Other X X X Other Other
DOUT DIN High Z High Z High Z DOUT DIN High Z High Z High Z
2,3,4 2,4 5,6 5,6 5,6 2,4 2,4 4,5,6 4,5,6 4,5,7
FLASH must be in High Z Write SRAM Standby Any FLASH mode is allowable Output Disable Data Retention L same as a standby L H
Notes: 1. Two devices cannot drive the memory bus at the same time. 2. To place the SRAM into data retention mode, lower the S-VCC signal to the VDR range, as specified.
2.1.2
Output Disable
When F-OE# and S-OE# are deasserted, the SCSP output signals are placed in a high-impedance state.
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Datasheet
C3 SCSP Flash Memory
2.1.3
Standby
When F-CE# and S-CS1# or S-CS2 are deasserted, the SCSP enters a standby mode, which substantially reduces device power consumption. In standby mode, outputs are placed in a highimpedance state independent of F-OE# and S-OE#. If the flash memory device is deselected during a program or erase operation, the flash memory continues to consume active power until the program or erase operation is complete.
2.1.4
Flash Reset
The flash memory device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After returning from reset, a time tPHQV is required until outputs are valid. A delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored.
* The flash memory device defaults to read array mode. * The status register is set to 80h. * The read configuration register defaults to asynchronous reads.
If RP# is taken low during a block erase or program operation, the operation aborts and the memory contents at the aborted location are no longer valid.
2.1.5
Write * Writes to flash memory occur when both F-CE# and F-WE# are asserted and F-OE# is
deasserted.
* Writes to SRAM occur when both S-CS1# and S-WE# are asserted and S-OE# and S-CS2 are
deasserted. Commands are written to the flash memory Command User Interface (CUI), using standard microprocessor write timings to control flash memory operations. The CUI does not occupy an addressable memory location within the flash memory device. The address and data buses are latched on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 on page 33 and Figure 7 on page 35 for read and write waveforms.)
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
3.0
Flash Memory Modes of Operation
The flash memory has four read modes:
* * * *
Read array Read configuration Read status CFI query
The write modes are:
* Program * Erase
Three additional modes are available only during suspended operations:
* Erase suspend to program * Erase suspend to read * Program suspend to read
These modes are reached using the commands summarized in Table 5 "Flash Memory Command Definitions" on page 19.
3.1
Read Array (FFh)
When F-RP# transitions from VIL (reset) to VIH, the flash memory device defaults to read array mode and responds to the read control inputs without additional CUI commands. In addition, the address of the desired location must be applied to the address balls. If the flash memory device is not in read array mode, such as after a program or erase operation, the Read Array command (FFh) must be written to the CUI before array reads can take place.
3.2
Read Identifier (90h)
The Read Configuration mode outputs three types of information:
* Manufacturer/device identifier * Block locking status * Protection register
1. To switch the flash memory device to this mode, write the read configuration command (90h). In this mode, read cycles from addresses shown in Table 4 "Read Configuration Table" on page 15 retrieve the specified information. 2. To return to read array mode, write the Read Array command (FFh).
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Datasheet
C3 SCSP Flash Memory
Table 4.
Read Configuration Table
Item Manufacturer Code (x16) Device ID (See Appendix D) Block Lock Configuration Address 0x00000 0x00001 0xXX002 Data 0x0089 ID LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1 0x80 0x81-0x88 PR-LK PR 3 1, 2 Notes
* Block Is Unlocked * Block Is Locked * Block Is Locked-Down
Protection Register Lock Protection Register (x16)
Notes: 1. See Section 3.7 for valid lock status outputs. 2. "XX" specifies the block address of lock configuration being read. 3. See Section 3.8 for protection register information.
Intel reserves other locations within the configuration address space for future use.
3.3
Read Status Register (70h)
The status register indicates the status of device operations, and the success/failure of that operation. 1. After you issue the Read Status Register (70h) command, subsequent reads output data from the status register until another command is issued. 2. To return to reading from the array, issue a Read Array (FFh) command. The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a Read Status Register command. The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever occurs last. Latching on the falling edge prevents possible bus errors that might occur if status register contents change while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status register does not indicate completion of a program or erase operation. When the WSM is active, SR7 indicates the status of the WSM. The remaining bits in the status register indicate whether the WSM was successful in performing the desired operation (see Table 6 "Flash Memory Status Register Definition" on page 19).
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
3.3.1
Clear Status Register (50h)
The WSM sets status bits 1 through 7 to a 1 value, and clears bits 2, 6 and 7 to a 0 value. However, WSM cannot clear status bits 1 or 3 through 5 to a 0 value. Because bits 1, 3, 4, and 5 indicate various error conditions, only the Clear Status Register (50h) command can clear these bits. If the system software controls resetting these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine whether an error occurred during that series.
* Clear the status register before beginning another command or sequence. * A Read Array command must be issued before data can be read from the memory array. * Resetting the flash memory device also clears the status register.
3.4
CFI Query (98h)
The CFI query mode outputs Common Flash Interface (CFI) data when the flash memory device is read. The CFI data structure contains information such as:
* * * *
block size density command set electrical specifications
1. To access this mode, write the CFI Query Command (98h). In this mode, read cycles from addresses shown in Appendix B, "CFI Query Structure" retrieve the specified information. 2. To return to read array mode, write the Read Array command (FFh).
3.5
Word Program (40h/10h)
Programming uses a two-write sequence. 1. The Program Setup command (40h) is written to the CUI. 2. A second write specifies the address and data to program. 3. The WSM executes a sequence of internally timed events to program desired bits of the addressed location 4. The WSM then verifies that the bits are sufficiently programmed. Programming the memory changes the value of specific bits within an address to 0.
Note:
If you attempt to program a 1 value, the memory cell contents do not change and no error occurs.
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Datasheet
C3 SCSP Flash Memory
The status register indicates programming status:
* While the program sequence executes, status bit 7 has a 0 value. * To poll the status register, toggle either F-CE# or F-OE#.
While programming, the only valid commands are:
* Read Status Register * Program Suspend * Program Resume
1. When programming is complete, check the program status bits. -- If the programming operation was unsuccessful, status register but SR.4 is set to indicate a program failure. -- If SR.3 is set, then F-VPP was not within acceptable limits, and the WSM did not execute the program command. -- If SR.1 is set, a program operation was attempted on a locked block and the operation aborted. 2. Clear the status register before attempting the next operation. Any CUI instruction can follow after programming is completed. 3. To prevent inadvertent status register reads, reset the CUI to read array mode.
3.5.1
Suspending and Resuming Program (B0h/D0h)
The Program Suspend command halts an in-progress program operation, so that data can be read from other locations of memory. 1. After the programming process starts, write the Program Suspend command to the CUI. -- This command requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). -- The flash memory device continues to output status register data after the Program Suspend command is written. 2. Poll status register bits SR.7 and SR.2 to determine when the program operation has been suspended (both are set to 1).
Note:
tWHRH1/tEHRH1 specifies the program suspend latency. A Read Array command can be written to the CUI to read data from any block other than the suspended block. The only other valid commands, while program is suspended, are:
* * * *
Read Status Register Read Configuration CFI Query Program Resume.
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C3 SCSP Flash Memory
After the Program Resume command is written to the flash memory:
* WSM continues the programming process. * Status register bits SR.2 and SR.7 are automatically cleared. * The flash memory device automatically outputs status register data when read (see Appendix
A, "Program/Erase Flowcharts"). Note: F-VPP must remain at the same F-V PP level used for program while in program suspend mode. F-RP# must also remain at V IH.
3.6
Block Erase (20h)
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If F-VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that F-V PP supply voltage was not within acceptable limits. After an erase operation, clear the status register (50h) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.6.1
Suspending and Resuming Erase (B0h/D0h)
An erase operation can take several seconds to complete, therefore, the Erase Suspend command is provided to allow erase-sequence interruption in order to read data from, or program data to, another block in memory. Once an erase sequence has started, writing the Erase Suspend command to the CUI causes the device to suspend the erase sequence at a predetermined point in the erase algorithm. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 5.7, "Flash Erase and Program Timings" on page 31. When an erase operation has been suspended, a Word Program or Read operation can be performed within any block, except the block that is in an erase suspend state. An erase operation cannot be nested within another erase suspend operation. A suspended erase operation cannot resume until the nested program operation has completed. Read Array, Read Status Register, Clear Status Register, Read Identifier, CFI Query, Erase Resume, are all valid commands during Erase Suspend. Additionally, Program, Program Suspend, Program Resume, Lock Block, Unlock Block and Lock-Down Block are valid commands during Erase Suspend. To resume an erase suspend operation, issue the Resume command. The Resume command can be written to any device address. When a program operation is nested within an Erase Suspend operation and the Program Suspend command is issued, the device will suspend the program
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Datasheet
C3 SCSP Flash Memory
operation. When the resume command is issued, the device will resume the program operation first. Once the nested program operation is completed, an additional Resume command is required to complete the block operation.
Table 5.
Flash Memory Command Definitions
First Bus Cycle Command Note Operation Address X X X X X X X X X X X X X X Data FFh 90h 98h 70h 50h 40h/10h 20h B0h D0h 60h 60h 60h C0h C0h Write Write Write Write Write BA BA BA PA PA 01h D0h 2Fh PD FFFD Write Write PA BA PD D0h Read Read Read IA QA X ID QD SRD Operation Address Data 1 1, 2 1, 2 1 1 1, 3 1 1 1 1 1, 4 1 1 1 Write Write Write Write Write Write Write Write Write Write Write Write Write Write Second Bus Cycle
Read Array Read Identifier CFI Query Read Status Register Clear Status Register Word Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Register Program Lock Protection Register
X = Don't Care SRD = Status Register Data
PA = Program Address PD = Program Data
BA = Block Address
IA = Identifier Address ID = Identifier Data
QA = Query Address QD = Query Data
Notes: 1. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or V IH, to minimize current draw. 2. Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query information, respectively. 3. Either 40h or 10h command is valid, but the Intel standard is 40h. 4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Table 6.
WSMS 7
Flash Memory Status Register Definition
ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0
Datasheet
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C3 SCSP Flash Memory
Bit Number SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming
NOTES: Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to 1. ESS bit remains set to 1 until an Erase Resume command is issued. When this bit is set to 1, WSM has applied the max. number of erase pulses and is still unable to verify successful block erasure. When this bit is set to 1, WSM has attempted but failed to program a word/byte. The F-V PP status bit does not provide continuous indication of VPP level. The WSM interrogates F-VPP level only after the Program or Erase command sequences have been entered, and informs the system if F-VPP has not been switched on. The F-VPP is also checked before the operation is verified by the WSM. The F-VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1 min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to 1. PSS bit remains set to 1 until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register.
SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP Low Detect, Operation Abort 0 = F-VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Note:
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
3.7
Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked with no latency, which enables instant code and data protection. This locking offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term "state [XYZ]" will be used to specify locking states; e.g., "state [001]," where X = value of WP#, Y = bit DQ1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 8 "Block Locking State Transitions" on page 23 defines all of these possible locking states.
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Datasheet
C3 SCSP Flash Memory
3.7.1
Block Locking Operation Summary
The following concisely summarizes the locking functionality. All blocks are locked when powered-up, and can be unlocked or locked with the Unlock and Lock commands.
* The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0. * When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down
blocks.
* When WP# returns to 0, locked-down blocks return to Lock-Down. * Lock-Down is cleared only when the device is reset or powered-down.
The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 8 on page 23, and a flowchart for locking operations is shown in Figure 19 on page 50.
3.7.2
Locked State
The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. Unlocked blocks can be locked issuing the "Lock" command sequence, 60h followed by 01h.
3.7.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60h followed by D0h.
3.7.4
Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence, 60h followed by 2Fh. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function is dependent on the WP# input ball. When WP# = 0, blocks in LockDown [011] are protected from program, erase, and lock status changes. When WP# = 1, the LockDown function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be re-locked [111] and unlocked [110] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state.
Datasheet
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C3 SCSP Flash Memory
3.7.5
Reading Lock Status for a Block
The lock status of every block can be read in the configuration read mode of the device. To enter this mode, write 90h to the device. Subsequent reads at Block Address + 00002 will output the lock status of that block. The lock status is represented by the least significant outputs, DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates LockDown status and is set by the Lock-Down command. It cannot be cleared by software, only by device reset or power-down.
Table 7.
Block Lock Status
Item Block Lock Configuration * Block Is Unlocked * Block Is Locked * Block Is Locked-Down Address XX002 Data LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1
3.7.6
Locking Operation During Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the erase suspend command (B0h), then check the status register until it indicates that the erase operation has been suspended. Next write the desired lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend.
3.7.7
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Since locking changes are performed using a two cycle command sequence, e.g., 60h followed by 01h to lock a block, following the Configuration Setup command (60h) with an invalid command will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1, and will remain at 1 after the erase is resumed. When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend.
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Datasheet
C3 SCSP Flash Memory
Table 8.
Block Locking State Transitions
Current State Erase/ Program Allowed? Yes Yes No No No Yes No Next State after Command Input Lock Go To [001] Go To [101] - - - Go To [111] Unlock - - Go To [000] Go To [100] - - Go To [110] Lock-Down Go To [011] Go To [111] Go To [011] Go To [111] - Go To [111] -
WP# 0 1 0 1 0 1 1
DQ1 0 0 0 0 1 1 1
DQ0 0 0 1 1 1 0 1
Name Unlocked Unlocked Locked (Default) Locked Locked-Down Lock-Down Disabled
Notes: 1. "-" indicates no change in the current state. 2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ 1, and Z = DQ0. The current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ 0 indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0). 3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the recommended default. 4. The "Erase/Program Allowed?" column shows whether erase and program operations are enabled (Yes) or disabled (No) in that block's current locking state. 5. The "Lock Command Input Result [Next State]" column shows the result of writing the three locking commands (Lock, Unlock, Lock-Down) in the current locking state. For example, "Goes To [001]" would mean that writing the command to a block in the current locking state would change it to [001]. 6. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
3.8
128 Bit Protection Register
The C3 SCSP architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution.
3.8.1
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses shown in Appendix E retrieve the specified information. To return to read array mode, write the Read Array command (FFh).
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C3 SCSP Flash Memory
3.8.2
Programming the Protection Register (C0h)
The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection Program Setup command, C0h. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Appendix E. See Figure 20 "Protection Register Programming Flowchart" on page 51. Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to 1). Attempting to program or to a previously locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).
3.8.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program FFFDh to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. A Protection Program command to locked words will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). The protection register lockout state is not reversible.
Figure 3.
Protection Register Memory Map
88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H PR-LOCK
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Datasheet
C3 SCSP Flash Memory
4.0
4.1
Power and Reset Considerations
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up F-VCC, F-VCCQ and S-VCC together. Conversely, F-VCC, F-VCCQ and S-VCC must power-down together. It is also recommended to power-up F-VPP with or slightly after F-VCC. Conversely, F-VPP must power down with or slightly before F-VCC. If F-VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should attain FVCCMin before applying F-VCCQ and F-VPP. Device inputs should not be driven before supply voltage = F-VCCMin. Power supply transitions should only occur when F-RP# is low.
4.2
Additional Flash Features
C3 SCSP products provide in-system programming and erase in the 1.65 V-3.3 V range. For fast production programming, it also includes a low-cost, backward-compatible 12 V programming feature.
4.2.1
Improved 12 Volt Production Programming
When F-VPP is between 1.65 V and 3.3 V, all program and erase current is drawn through the F-VCC signal. Note that if F-VPP is driven by a logic signal, VIH min = 1.65 V. That is, F-VPP must remain above 1.65 V to perform in-system flash modifications. When F-VPP is connected to a 12 V power supply, the device draws program and erase current directly from the F-VPP signal. This eliminates the need for an external switching transistor to control the voltage F-VPP. Figure 12 "Example Power Supply Configurations" on page 43 shows examples of how the flash power supplies can be configured for various usage models. The 12 V F-VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to F-VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-V PP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
4.2.2
F-VPP VPPLK for Complete Protection
In addition to the flexible block locking, the F-VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When F-VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set.
Datasheet
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C3 SCSP Flash Memory
5.0
5.1
Warning:
Electrical Specifications
Absolute Maximum Ratings
Stressing the device beyond the Absolute Maximum Ratings in Table 9 might cause permanent damage. These are stress ratings only. Do not operate the flash memory device beyond the Operating Conditions in Table 10. Extended exposure beyond these Operating Conditions might affect device reliability.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Table 9.
Absolute Maximum Ratings
Parameter Extended Operating Temperature During Read -25C to +85C During Flash Block Erase and Program Temperature under Bias Storage Temperature Voltage on Any Ball (except F-VCC /F-VCCQ / S-VCC and F-VPP) with Respect to GND F-VPP Voltage (for Block Erase and Program) with Respect to GND F-VCC / F-VCCQ / S-VCC Supply Voltage with Respect to GND Output Short Circuit Current -65C to +125C -0.5 V to +3.3 V -0.5 V to +13.5 V -0.2V to +3.3 V 100 mA 3 1 1,2,4 Maximum Rating Notes
Notes: 1. Minimum DC voltage is -0.5 V on input/output balls. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output balls is F-VCC / F-VCCQ / S-VCC + 0.5 V which, during transitions, may overshoot to F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns. 2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 3. F-VPP voltage is normally 1.65 V-3.3 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/ erase. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for details 4. Output shorted for no more than one second. No more than one output shorted at a time.
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Datasheet
C3 SCSP Flash Memory
5.2
Table 10.
Operating Conditions
Maximum Operating Conditions
Symbol TCASE VCC / V CCQ VPP1 VPP2 Cycling Block Erase Cycling Parameter Operating Temperature F-VCC /F-VCCQ /S-VCC Supply Voltage Supply Voltage 1 1 1, 2 2 Notes Min -25 2.7 1.65 11.4 100,000 Max +85 3.3 3.3 12.6 Units C Volts Volts Volts Cycles
Notes: 1. F-VCC/F-VCCQ must share the same supply. F-V CC/S-VCC must share the same supply when not in data retention. 2. Applying F-VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for details.
5.3
Capacitance
TCASE = +25C, f = 1 MHz
Table 11.
Capacitance
Sym CIN COUT Note: Parameter Input Capacitance Output Capacitance Sampled, not 100% tested. Notes 1 1 Typ 16 20 Max 18 22 Units pF pF Conditions VIN = 0 V VOUT = 0 V
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C3 SCSP Flash Memory
5.4
Table 12.
Symbol
DC Characteristics
DC Characteristics (Sheet 1 of 2)
2.7 V - 3.3 V Parameter Device Note Typ Max 2 0.2 10 10 25 A 1 7 15 F-V CC = VCC Max F-CE# = F-RP# = VCC F-WP# = VCC or GND VIN = VCC Max or GND S-VCC = VCC Max S-CS1# = VCC, S-CS2 = VCC or S-CS2 = GND 1 1 1 7 15 25 25 F-VCC = VCC Max A 1 7 15 VIN = VCC Max or GND F-RP# = GND 0.2 V A A VIN = VCC Max or GND A A F-VCC/S-VCC = VCC Max VIN = VCC Max or GND F-VCC/S-VCC = VCC Max VIN = VCC Max or GND Unit Test Conditions
ILI ILO
Input Load Current Output Leakage Current
Flash/ SRAM Flash/ SRAM 0.25m Flash 0.13m and 0.18m Flash 2-Mb SRAM 4-Mb SRAM 8-Mb SRAM 0.25m Flash
1 1 1
ICCS
VCC Standby Current
1
-
10
A
ICCD
VCC Deep Power-Down Current
0.13m and 0.18m Flash 2-Mb SRAM 4-Mb SRAM 8-Mb SRAM
1 1 1 1 1 1 1,2
10
7 10 10 40 45 50 18
mA mA mA mA mA mA mA
ICC
Operating Power Supply Current (cycle time = 1 s)
IIO = 0 mA, S-CS1# = VIL S-CS2 = S-WE# = V IH VIN = VIL or VIH
ICC2
Operating Power Supply Current (min cycle time)
2-Mb SRAM 4-Mb SRAM 8-Mb SRAM 0.25m Flash
Cycle time = Min, 100% duty, IIO = 0 mA, S-CS1# = V IL, S-CS2 = VIH, VIN = VIL or VIH
F-V CC = VCC Max F-OE# = VIH , F-CE# = VIL f = 5 MHz, IOUT = 0 mA VIN = VIL or V IH
ICCR
VCC Read Current
0.13m and 0.18m Flash
1,2
9
18
mA
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C3 SCSP Flash Memory
Table 12.
Symbol
DC Characteristics (Sheet 2 of 2)
2.7 V - 3.3 V Parameter Device Note Typ 18 Max 55 22 45 15 15 25 A 1,3,4 7 15 F-CE# = VCC, Program Suspend in Progress mA mA mA mA A F-VPP = VPP1 Program in Progress F-VPP = VPP2 (12 V) Program in Progress F-VPP = VPP1 Erase in Progress F-VPP = VPP2 (12 V) Erase in Progress F-CE# = VCC, Erase Suspend in Progress Unit Test Conditions
ICCW
VCC Program Current
Flash
1,3 8 16
ICCE
VCC Erase Current
Flash
1,3 8
ICCES
VCC Erase Suspend Current
Flash 0.25m Flash
1,3,4 1,3,4
7 10
ICCWS
VCC Program Suspend Current
0.13m and 0.18m Flash Flash Flash Flash
IPPD IPPS IPPR
F-VPP Deep Power-Down Current F-VPP Standby Current F-VPP Read Current
1 1 1 1,2
0.2 0.2 2 50 0.05
5 5 15 200 0.1 22 0.1 5 200 5 200
A A A A mA mA ma A A A A
F-RP# = GND 0.2 V F-VPP VCC F-VPP VCC F-VPP VCC F-VPP VCC F-VPP =VPP1 Program in Progress F-VPP = VPP2 (12 V) Program in Progress F-VPP = VPP1 Erase in Progress F-VPP = VPP1 Erase Suspend in Progress F-VPP = VPP2 (12 V) Erase Suspend in Progress F-VPP = VPP1 Program Suspend in Progress F-VPP = VPP2 (12 V) Program Suspend in Progress
IPPW
F-VPP Program Current
Flash
1,2 8
IPPE
F-VPP Erase Current
Flash
1,2
0.05 0.2
IPPES
F-VPP Erase Suspend Current
Flash
1,2 50 0.2
IPPWS
F-VPP Program Suspend Current
Flash
1,2 50
Notes: 1. 2. 3. 4.
All currents are in RMS unless otherwise noted. Typical values at nominal F-VCC/S-VCC , TCASE = +25 C. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). Sampled, not 100% tested. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 13.
Symbol
DC Characteristics
2.7 V - 3.3 V Parameter Device Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash Flash 1 1 1,2 Flash Flash 1.65 11.4 1.5 1.2 Note Min Max 0.6 V CC +0.2 0.10 V V V V 1.0 3.3 12.6 V V V V F-VCC /S-VCC = VCC Min IOL = 100 A F-VCC /S-VCC = VCC Min IOH = -100 A Complete Write Protection Units Test Conditions
VIL V IH V OL V OH VPPLK VPP1 VPP2 V LKO VLKO2
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lock-Out Voltage F-VPP during Program / Erase Operations VCC Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage
-0.2 2.3 -0.10 VCC - 0.1
Notes: 1. Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outside the valid F-Vpp ranges of VPP1 and VPP2. 2. Applying F-Vpp = 11.4V-12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-Vpp may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for details.
Figure 4.
Input/Output Reference Waveform
VCC INPUT 0.0
Note: AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%-90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin.
VCC 2
TEST POINTS
VCC 2
OUTPUT
Figure 5.
Test Configuration
Device Under Test
Out CL
Note:
CL includes jig capacitance.
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Datasheet
C3 SCSP Flash Memory
Flash Test Configuration Component Values Table
Test Configuration 2.7 V-3.3 V Standard Test CL (pF) 50
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
5.5
Table 14.
Flash AC Characteristics.
Flash AC Characteristics--Read Operations
Density Product -70 16-Mbit -90 -110 2.7 V - 3.3 V Mi n 70 70 1 1 70 20 150 2 2 2 2 0 0 20 20 0 0 25 20 Ma x Mi n 90 90 90 30 150 0 0 25 20 Ma x Mi n 110 110 110 30 150 0 0 20 20 Ma x Ma x Ma x ns 90 90 20 150 0 0 20 20 ns ns ns ns ns ns ns ns -70 32-Mbit -90 Uni t
#
Sym
Parameter
Voltage Range Note
Min 70
Min 90
R1 R2 R3 R4 R5 R6 R7 R8 R9 R1 0
tAVAV tAVQ
V
Read Cycle Time Address to Output Delay F-CE# to Output Delay F-OE# to Output Delay F-RP# to Output Delay F-CE# to Output in Low Z F-OE# to Output in Low Z F-CE# to Output in High Z F-OE# to Output in High Z Output Hold from Address
70 70 20 150
tELQ
V
tGLQ
V
tPHQ
V
tELQ
X
tGLQ
X
tEHQ
Z
tGHQ
Z
tOH
F-CE#, or F-OE# Change, Whichever Occurs First
2
0
0
0
0
0
ns
Notes: 1. 2. 3. 4.
F-OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV Sampled, but not 100% tested. See Figure 6 "AC Waveform: Flash Read Operations" on page 33. See Figure 4, "Input/Output Reference Waveform" on page 28 for timing measurements and maximum allowable input slew rate.
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Datasheet
C3 SCSP Flash Memory
Figure 6.
AC Waveform: Flash Read Operations
Device and Address Selection Address Stable R1 Data Valid
VIH ADDRESSES (A) VIL CE# (E) VIH VIL VIH OE# (G) VIL VIH WE# (W) VIL VOH DATA (D/Q) VOL RP#(P) VIH VIL High Z
Standby
R8
R9 R7 R6 R2 R5 R4 R3 Valid Output High Z R10
5.6
Table 15.
Flash AC Characteristics--Write Operations
Flash AC Characteristics--Write Operations (Sheet 1 of 2)
Density Product -70 16-Mbit -90 110 32-Mbit -70 -90 Uni t
#
Sym
Parameter
Voltage Range Note Mi n 150 0 1 2 2 45 40 50 0 2 2 1 0 0 25
2.7 V - 3.3 V Mi n 150 0 60 50 60 0 0 0 30
Min 150 0 70 60 70 0 0 0 30
Min 150 0 45 40 50 0 0 0 25
Min 150 0 60 40 60 0 0 0 30 ns ns ns ns ns ns ns ns ns
W1 W2 W3 W4 W5 W6 W7 W8 W9
tPHWL tPHEL tELWL tWLEL tELEH tWLWH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL
F-RP# High Recovery to F-WE# (F-CE#) Going Low F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low F-WE# (F-CE#) Pulse Width Data Setup to F-WE# (F-CE#) Going High Address Setup to F-WE# (F-CE#) Going High F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High Data Hold Time from F-WE# (F-CE#) High Address Hold Time from F-WE# (F-CE#) High F-WE# (F-CE#) Pulse Width High
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 15.
Flash AC Characteristics--Write Operations (Sheet 2 of 2)
Density Product -70 16-Mbit -90 110 32-Mbit -70 -90 Uni t
#
Sym
Parameter
Voltage Range Note Mi n 200 0
2.7 V - 3.3 V Mi n 200 0
Min 200 0
Min 200 0
Min 200 0 ns ns
W1 0 W11
tVPWH tVPEH tQVVL
F-VPP Setup to F-WE# (F-CE#) Going High F-VPP Hold from Valid SRD
3 3
Notes: 1. Write pulse width (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or F-WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from F-CE# or F-WE# going high (whichever goes high first) to F-CE# or F-WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 5 "Flash Memory Command Definitions" on page 19 for valid AIN or DIN. 3. Sampled, but not 100% tested.
See Figure 4 "Input/Output Reference Waveform" on page 30 for timing measurements and maximum allowable input slew rate. See Figure 7 "AC Waveform: Flash Program and Erase Operations" on page 35.
5.7
Table 16.
Symbol tBWPB tBWMB tWHQV1 / tEHQV1
Flash Erase and Program Timings(1)
Flash Erase and Program Timings
F-VPP Parameter Note 4-KW Parameter Block Program Time (Word) 32-KW Main Block Program Time (Word) 0.25 m Word Program Time 0.13 m and 0.18 m Word Program Time 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 3 3 Typ(1) 0.10 0.8 22 12 0.5 1 5 5 Max 0.30 2.4 200 200 4 5 10 20 Typ(1) 0.03 0.24 8 8 0.4 0.6 5 5 Max 0.12 1 185 s 185 4 5 10 20 s s s s s s 1.65 V- 3.3 V 11.4 V- 12.6 V Unit
tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time (Word) tWHQV3 / tEHQV3 32-KW Main Block Erase Time (Word) tWHRH1 / tEHRH1 Program Suspend Latency tWHRH2 / tEHRH2 Erase Suspend Latency
Notes: 1. Typical values measured at TCASE = +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested.
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Datasheet
C3 SCSP Flash Memory
Figure 7.
AC Waveform: Flash Program and Erase Operations
A B AIN C AIN W5 W6 W9 W8 (Note 1) D E F
VIH
ADDRESSES [A]
VIL VIH
CE#(WE#) [E(W)]
VIL VIH W2
OE# [G]
VIL VIH
WE#(CE#) [W(E)]
(Note 1)
VIL VIH
DATA [D/Q]
W3 W4
High Z
W7 DIN DIN
VIL
W1
Valid SRD
DIN
RP# [P]
VIH VIL VIH
WP#
VIL VPPH 2 VPPH1 VPPLK VIL
W10
W11
V
PP
[V]
Notes: 1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading Status Register Data. 2. F-VCC Power-Up and Standby. 3. Write Program or Erase Setup Command. 4. Write Valid Address and Data (for Program) or Erase Confirm Command. 5. Automated Program or Erase Delay. 6. Read Status Register Data (SRD): reflects completed program/erase operation. 7. Write Read Array Command.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
5.8
Figure 8.
Flash Reset Operations
AC Waveform: Reset Operation
VIH VIL
RP# (P)
t PLPH (A) Reset during Read Mode
tPHQV tPHWL tPHEL
Abort Complete
t PLRH
RP# (P)
VIH V IL
t PHQV t PHWL t PHEL
t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep Complete PowerDown
RP# (P)
VIH V IL
t PLRH
t PHQV t PHWL t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
Table 17.
Reset Specifications(1)
F-VCC 2.7 V - 3.3 V Symbol Parameter F-RP# Low to Reset during Read (If F-RP# is tied to VCC , this specification is not applicable) F-RP# Low to Reset during Block Erase F-RP# Low to Reset during Program Note Min tPLPH tPLRH1 tPLRH2 2,4 3,4 3,4 100 22 12 Max ns s s Unit
Notes: 1. See Section 2.1.4, "Flash Reset" on page 13 for a full description of these conditions. 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested.
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Datasheet
C3 SCSP Flash Memory
5.9
Table 18.
SRAM AC Characteristics--Read Operations
SRAM AC Characteristics--Read Operations(1)
Density # Sym Parameter Voltage Range Note R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Note: 1. 2. 3. 4. tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH tBLZ tBHZ Read Cycle Time Address to Output Delay S-CS1#, S-CS2 to Output Delay S-OE# to Output Delay S-UB#, LB# to Output Delay S-CS1#, S-CS2 to Output in Low Z S-OE# to Output in Low Z S-CS1#, S-CS2 to Output in High Z S-OE# to Output in High Z Output Hold from Address, S-CS1#, S-CS2, or S-OE# Change, Whichever Occurs First S-UB#, S-LB# to Output in Low Z S-UB#, S-LB# to Output in High Z 3 3 2,3 3 2,3,4 3,4 2/4/8-Mbit 2.7 V- 3.3 V Min 70 - - - - 5 0 0 0 0 0 0 Max - 70 70 35 70 - - 25 25 - - 25 ns ns ns ns ns ns ns ns ns ns ns ns Unit
See Figure 9 "AC Waveform: SRAM Read Operations" on page 38. At any given temperature and voltage condition, tHZ (Max) is less than and tLZ (Max) both for a given device and from device to device interconnection. Sampled, but not 100% tested. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Figure 9.
AC Waveform: SRAM Read Operations
Device Address Selection Address Stable VIL VIH R1
Standby VIH
Data Valid
ADDRESSES (A)
CS1# (E1) CS2 (E2)
VIL VIH VIL R2 VIH VIL R9 R4 VIL R7 High Z R6 Valid Output R11 R5 R12 R10 High Z VOH VOL VIH VIH R3 R8
OE# (G)
WE# (W)
VIH
DATA (D/Q)
UB#, LB#
5.10
Table 19.
SRAM AC Characteristics--Write Operations
SRAM AC Characteristics--Write Operations(1,2)
Density # Sym Parameter Volt Note W1 W2 W3 W4 W5 W6 W7 tWC tAS tWP tDW tAW tCW tDH Write Cycle Time Address Setup to S-WE# (S-CS1#) and S-UB#, S-LB# Going Low S-WE# (S-CS 1#) Pulse Width Data to Write Time Overlap Address Setup to S-WE# (S-CS1#) Going High S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going High Data Hold Time from S-WE# (S-CS1#) High 3 4 2/4/8-Mbit 2.7 V - 3.3 V Min 70 0 55 30 60 60 0 Max - - - - - - - ns ns ns ns ns ns ns Unit
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Datasheet
C3 SCSP Flash Memory
Table 19.
SRAM AC Characteristics--Write Operations(1,2)
Density # Sym Parameter Volt Note W8 W9 tWR tBW Write Recovery S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High 5 2/4/8-Mbit 2.7 V - 3.3 V Min 0 60 Max - - ns ns Unit
Notes: 1. See Figure 10 "AC Waveform: SRAM Write Operations" on page 39. 2. A write occurs during the overlap (tWP) of low S-CS 1# and low S-WE#. A write begins when S-CS1# goes low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously asserting S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes high and S-WE# goes high. The tWP is measured from the beginning of write to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWP is measured from S-CS1# going low to end of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as SCS1# or S-WE# going high.
Figure 10.
AC Waveform: SRAM Write Operations
Device Address Selection Address Stable VIL VIH W1 W8
Standby VIH
ADDRESSES (A)
CS1# (E1) CS2 (E2)
VIL VIH VIL VIH VIL W5 W3 W6
OE# (G)
WE# (W)
VIH VIL
W7 W4 High Z High Z
DATA (D/Q)
VOH VOL
Data In W9
W2 VIH
UB#, LB#
VIH
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
5.11
Table 20.
Sym VDR
SRAM Data Retention Characteristics--Extended Temperature
SRAM Data Retention Characteristics(1)--Extended Temperature
Parameter S-VCC for Data Retention Deep Retention Current 8-Mbit Deep Retention Current 4-Mbit Deep Retention Current 2-Mbit 2 - - 0 tRC - - - - 5 4 - - A A ns ns See Data Retention Waveform Note Min 1.5 - Typ - - Max 3.3 6 Unit V A S-VCC = 1.5 V CS1# VCC - 0.2 V Test Conditions CS1# VCC - 0.2 V
IDR
tSDR tRDR
Data Retention Set-up Time Recovery Time
Notes: 1. Typical values at nominal S-VCC, TCASE = +25 C. 2. S-CS1# VCC - 0.2 V, S-CS2 VCC - 0.2 V (S-CS1# controlled) or S-CS2 0.2 V (S-CS2 controlled).
Figure 11.
SRAM Data Retention Waveform
tSDR Data Retention Mode tRDR
CS1# Controlled VCC 3.0/2.7V
CS1# (E1) 2.2V
VDR GND CS2 Controlled tSDR VCC 3.0/2.7V Data Retention Mode tRDR
CS2 (E2)
VDR 0.4V GND
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Datasheet
C3 SCSP Flash Memory
6.0
Migration Guide Information
Typically, it is important to discuss footprint migration compatibility between a new product and existing products. In this specific case, the SCSP allows the system designer to remove two separate memory footprints for individual flash and SRAM and replace them with a single footprint, thus resulting in an overall reduction in board space required. This implies that a new printed circuit board would be used to take advantage of this feature. Since the flash in SCSP shares the same features as the C3 features, conversions from the C3 are described in AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory, order number 292216. Please contact your local Intel representation for detailed information about specific Flash + SRAM system migrations.
7.0
System Design Considerations
This section contains information that would have been contained in a product design guide in earlier generations. In an effort to simplify the amount of documentation, relevant system design considerations have been combined into this document.
7.1
Background
The C3 SCSP combines the features of the C3 flash memory architecture with a low-power SRAM to achieve an overall reduction in system board space. This enables applications to integrate security with simple software and hardware configurations, while also combining the system SRAM and flash into one common footprint. This section discusses how to take full advantage of the C3 SCSP.
7.1.1
Flash + SRAM Footprint Integration
The SCSP memory solution can be used to replace a subset of the memory subsystem within a design. Where a previous design may have used two separate footprints for SRAM and Flash, you can now replace with the industry-standard I-ballout of the SCSP device. This allows for an overall reduction in board space, which allows the design to integrate both the flash and the SRAM into one component.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
26 Aug 2005 41
C3 SCSP Flash Memory
7.1.2
C3 Flash Memory Features
C3 adds the following new features to Intel Advanced Boot Block architecture:
* Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking of any block with zero latency to protect code and data.
* A 128-bit Protection Register enables system security implementations. * Improved 12 V production programming simplifies the system configuration required to
implement 12 V fast programming.
* Common Flash Interface (CFI) provides component information on the chip to allow softwareindependent device upgrades. For more information on specific advantages of the C3, please see AP-658 Designing with the Advanced+ Boot Block Flash Memory Architecture.
7.2
Flash Control Considerations
The flash device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, F-VPP or F-VCC, powers-up first. Example flash power supply configurations are shown in Figure 12 "Example Power Supply Configurations" on page 43.
7.2.1
F-RP# Connected to System Reset
The use of F-RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting F-RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when F-VCC voltages are above V LKO. Since both F-WE# and F-CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until F-RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
7.2.2
F-VCC, F-VPP and F-RP# Transition
The CUI latches commands as issued by system software and is not altered by F-VPP or F-CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after F-VCC transitions above V LKO (Lockout voltage), is read array mode. After any program or block erase operation is complete (even after F-VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
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Datasheet
C3 SCSP Flash Memory
Figure 12.
Example Power Supply Configurations
System Supply
System Supply 12 V Supply 10 K 12 V Fast Programming Absolute Write Protection With V System Supply
(Note 1)
PP
VCC VPP
Prot# (Logic Signal)
VCC VPP
Low-Voltage Programming V PPLK Absolute Write Protection via Logic Signal System Supply
VCC VPP
VCC VPP
Low-Voltage Programming
12 V Supply Low Voltage and 12 V Fast Programming
Note:
1. A resistor can be used if the F-VCC supply can sink adequate current based on resistor value.
7.3
Noise Reduction
SCSP memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues for both the flash and SRAM:
* Standby current levels (ICCS) * Read current levels (ICCR) * Transient peaks produced by falling and rising edges of F-CE#, S-CS1#, and S-CS2.
Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each device should have a capacitors between individual power (F-VCC, F-VCCQ , F-VPP, S-VCC) and ground (GND) signals. High-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. Noise issues within a system can cause devices to operate erratically if it is not adequately filtered. In order to avoid any noise interaction issues within a system, it is recommended that the design contain the appropriate number of decoupling capacitors in the system. Noise issues can also be reduced if leads to the device are kept very short, in order to reduce inductance. Decoupling capacitors between VCC and VSS reduce voltage spikes by supplying the extra current needed during switching. Placing these capacitors as close to the device as possible reduces line inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically exhibit lower inductance. It is highly recommended that systems use a 0.1 f capacitor for each of the D9, D10, A10 and E4 grid ballout locations (see Figure 1 "66-Ball SCSP Package Ballout" on page 8 for ballout). These capacitors are necessary to avoid undesired conditions created by excess noise. Smaller capacitors can be used to decouple higher frequencies.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Figure 13.
Typical Flash + SRAM Substrate Power and Ground Connections
SUBSTRATE FLASH DIE SRAM DIE S-V SSQ F-V SSQ D3 S-V SS S-V CC D9 S-V CCQ F-V CC F-V CCQ E4 F-V PP F-V SS D10 A10 A9
H8
XX S-X F-X
Substrate connection to package ball SRAM die bond pad connection Flash die bond pad connection
Notes: 1. Substrate connections refer to ballout locations shown in Figure 1 "66-Ball SCSP Package Ballout" on page 8. 2. 0.1f capacitors should be used with D9, D10, A10and E4. 3. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS. 4. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
7.4
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at the same time. (See Table 2 "Intel(R) Advanced+ Boot Block SCSP Ball Descriptions" on page 9 for a summary of recommended operating modes.) Simultaneous operation of the can be summarized by the following:
* SRAM read/write are during a Flash Program or Erase Operation are allowed. * Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
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Datasheet
C3 SCSP Flash Memory
7.4.1
SRAM Operation during Flash "Busy"
This functionality provides the ability to use both the flash and the SRAM "at the same time" within a system, similar to the operation of two devices with separate footprints. This operation can be achieved by following the appropriate timing constraints within a system.
7.4.2
Simultaneous Bus Operations
Operations that require both the SRAM and Flash to be in active mode are disallowed. An example of these cases would include simultaneous reads on both the flash and SRAM, which would result in contention for the data bus. Finally, a read of one device while attempting to write to the other (similar to the conditions of direct memory access (DMA) operation) are also not within the recommended operating conditions. Basically, only one memory can drive the outputs out the device at one given point in time.
7.5
Printed Circuit Board Notes
The Intel SCSP will save significant space on your PCB by combining two chips into one BGA style package. Intel SCSP has a 0.8 mm pitch that can be routed on your Printed Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical. Unused balls in the center of the package are not populated to further increase the routing options. Standard surface mount process and equipment can be used for the Intel SCSP.
Figure 14.
Standard PCB Design Rules Can be Used with SCSP Device
Land Pad Diameter: 0.35 mm (0.0138 in) Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in) Trace Spaces: 0.160 mm (0.00625 in) Via Capture Pad: 0.51 mm (0.020 in) Via Drill Size: 0.25 mm (0.010 in)
Note:
Top View
7.6
System Design Notes Summary
The C3 SCSP allows higher levels of memory component integration. Different power supply configurations can be used within the system to achieve different objectives. At least three different 0.1 f capacitors should be used to decouple the devices within a system. SRAM reads or writes during a flash program or erase are supported operations. Standard printed circuit board technology can be used.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Appendix A Program/Erase Flowcharts
Figure 15. Automated Word Programming Flowchart
Start
Bus Operation Write Write Command Program Setup Program Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H
Program Address/Data
Read
Read Status Register
Standby
SR.7 = 1? Yes Full Status Check if Desired
No
Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful
If an error is detected, clear the status register before attempting retry or other error recovery.
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted
VPP Range Error 1 Programming Error
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
Attempted Program to Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.
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Datasheet
C3 SCSP Flash Memory
Figure 16.
Program Suspend/Resume Flowchart
Start
Bus Operation Write Command Program Suspend Read Status Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed Read Array Data = FFH Addr = X Read array data from block other than the one being programmed. Program Resume Data = D0H Addr = X
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.2 = 1
0
Standby
Write
0
Program Completed
Read
Write
Write FFH
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
0645_13
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
26 Aug 2005 47
C3 SCSP Flash Memory
Figure 17.
Automated Block Erase Flowchart
Start
Bus Operation Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H
Write
Erase Setup
Write D0H and Block Address
Write
Erase Confirm
Read
Read Status Register No
Suspend Erase Loop 0 Suspend Erase Yes
Standby
SR.7 = 1 Full Status Check if Desired
Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful Attempted Erase of Locked Block - Aborted
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted
VPP Range Error
Standby
1
Command Sequence Error
Standby
Standby
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.
0645_14
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Datasheet
C3 SCSP Flash Memory
Figure 18.
Erase Suspend/Resume Flowchart
Start
Bus Operation Write
Command Erase Suspend Read Status
Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.6 = 1
0
Standby
Write
Read Array
Data = FFH Addr = X Read array data from block other than the one being erased.
0
Erase Completed
Read
Write
Erase Resume
Write FFH
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Erase Resumed
Read Array Data
0645_15
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Figure 19.
Locking Operations Flowchart
Bus Operation Write
Start
Command Config. Setup
Comments Data = 60H Addr = X Data= 01H (Lock Block) D0H (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Data = 90H Addr = X Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ1, DQ0. (See Block Locking State Table for valid combinations.)
Write 60H (Configuration Setup) Write 01H, D0H, or 2FH
Write
Lock, Unlock, or Lockdown Read Configuration Block Lock Status
Write (Optional) Read (Optional) Standby (Optional)
Write 90H (Read Configuration)
Optional
Read Block Lock Status
Locking Change Confirmed? No Write FFh (Read Array)
Locking Change Complete
0645_16
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Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
Datasheet
C3 SCSP Flash Memory
Figure 20.
Protection Register Programming Flowchart
Start
Bus Operation Write Write
Command Protection Program Setup Protection Program
Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 = 1? Yes Full Status Check if Desired
No
Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPP Range Error 0,1 SR.1, SR.4 =
Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 V 0 0 1
PP
Low
Prot. Reg. Prog. Error Register Locked: Aborted
1
0
1
Protection Register Programming Error Attempted Program to Locked Register Aborted
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
1,1 SR.1, SR.4 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Program Successful
0645_17
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Appendix B CFI Query Structure
This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 21.
Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset 10: Device Address 11: 12: Code 51 52 59 ASCII Value "Q" "R" "Y"
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Datasheet
C3 SCSP Flash Memory
Table 22.
Example of Query Structure Output of x16 and x8 Devices
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A 0 10h 11h 12h 13h 14h 15h 16h 17h 18h ... 51 52 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "R" "Y" PrVendor ID # ID # ... Value
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below.
Table 23.
Offset 00h 01h (BA+2)h 04-0Fh 10h 1Bh 27h P
Query Structure
Sub-Section Name Manufacturer Code Device Code Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Block-specific information Reserved for vendor-specific information Command set ID and vendor data offset Device timing & voltage information Flash device layout Vendor-defined additional information specific to the Primary Vendor Algorithm Description 1 1 1,2 1 1 1 1 1,3 Notes
Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
B.3
Block Lock Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block.
Table 24.
Offset (BA+2)h
Block Status Register
Length 1 Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR.1 Block Lock-Down Status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Address BA+2: BA+2: Value --00 or --01 (bit 0): 0 or 1 Notes 1
BA+2: BA+2:
(bit 1): 0 or 1 (bit 2-7): 0
Note:
1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 25.
CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Addr. 10 11: 12: 13h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms 15h 2 Extended Query Table primary algorithm address 13: 14: 15: 16: 17h 2 Alternate vendor command set and control interface ID code 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists 17: 18: 19: 1A: Hex Code --51 --52 --59 --03 --00 --35 --00 --00 --00 --00 --00 Value "Q" "R" "Y"
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Datasheet
C3 SCSP Flash Memory
B.5
Table 26.
Offset
System Interface Information
System Interface Information
Length Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2 ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2 times typical "n" such that maximum block erase time-out = 2 times typical "n" such that maximum chip erase time-out = 2n times typical
n n n
Addr.
Hex Code --27
Value
1Bh
1
1B:
2.7 V
1Ch
1
1C:
--36
3.3 V
1Dh
1
1D:
--B4
11.4 V
1Eh 1Fh 1Bh
1 1 1
1E: 1F: 1B:
--C6 --05 --27
12.6 V 32 s 2.7 V
1Ch
1
1C:
--36
3.3 V
1Dh
1
1D:
--B4
11.4 V
1Eh 1Fh 1Bh
1 1 1
1E: 1F: 1B:
--C6 --05 --27
12.6 V 32 s 2.7 V
1Ch
1
1C:
--36
3.3 V
1Dh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
1D: 20: 21: 22: 23: 24: 25: 26:
--B4 --00 --0A --00 --04 --00 --03 --00
11.4 V n/a 1s n/a 512 s n/a 8s NA
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
B.6
n
Device Geometry Definition
Device Geometry Definition
Length 1 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 27: 28: 29: 2A: 2B: Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) --01 --00 --00 --00 0 x16 Code See Table Below
Table 27.
Offset 27h 28h
2Ah
2
"n" such that maximum number of bytes in write buffer = 2
n
2Ch
1
2C:
--02
2
2Dh
4
Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes
2D: 2E: 2F: 30:
31h
4
Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes
31: 32: 33: 34:
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Datasheet
C3 SCSP Flash Memory
Device Geometry Definition 16-Mbit Address -B 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: --15 --01 --00 --00 --00 --02 --07 --00 --20 --00 --1E --00 --00 --01 -T --15 --01 --00 --00 --00 --02 --1E --00 --00 --01 --07 --00 --20 --00 -B --16 --01 --00 --00 --00 --02 --07 --00 --20 --00 --3E --00 --00 --01 -T --16 --01 --00 --00 --00 --02 --3E --00 --00 --01 --07 --00 --20 --00 32-Mbit
B.7
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information.
Table 28.
Offset(1) P = 35h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h
Primary-Vendor Specific Extended Query (Sheet 1 of 2)
Length 3 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Addr. 35: 36: 37: 1 1 4 Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported 38: 39: 3A: 3B: 3C: 3D: Hex Code --50 --52 --49 --31 --30 --66 --00 --00 --00 No Yes Yes No Value "P" "R" "I" "1" "0"
bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 28.
Offset (1) P = 35h
Primary-Vendor Specific Extended Query (Sheet 2 of 2)
Length Description (Optional Flash Features and Commands) bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Page mode read supported bit 8 Synchronous read supported Addr. Hex Code Value No Yes Yes No No
bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 0 bit 8 = 0 3E: --01
(P+9)h
1
Supported functions after suspend: read array, status, query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend
bit 0 = 1 3F: 40: --03 --00
Yes
(P+A)h (P+B)h
2
Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active
bit 0 = 1 bit 1 = 1 41: --33
Yes Yes 3.3 V
(P+C)h
1
VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts
(P+D)h
1
42:
--C0
12.0 V
Table 29.
Offset (1) P = 35h (P+E)h (P+F)h
Protection Register Information
Length 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. 4 bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC -plane physical high address bits 16-23 = "n" such that 2n = factory pre- programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes Addr. 43: 44: Hex Code --01 --80 Value 01 80h
(P+10)h
45:
--00
00h
(P+11)h
46:
--03
8 byte
(P+12)h (P+13)h Note: Reserved for future use
47: 48:
--03
8 byte
1. The variable P is a pointer which is defined at CFI offset 15h.
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Datasheet
C3 SCSP Flash Memory
Appendix C Word-Wide Memory Map Diagrams
Table 30. 16, 32, and 64 Mbit Memory Addressing (Sheet 1 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 16-Mbit 32-Mbit 1FF0001FFFFF 1FE0001FEFFF 1FD0001FDFFF 1FC0001FCFFF 1FB0001FBFFF 1FA0001FAFFF 1F90001F9FFF 1F80001F8FFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 64-Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-Mbit Bottom Boot 32-Mbit 64-Mbit 3F80003FFFFF 3F00003F7FFF 3E80003EFFFF 3E00003E7FFF 3D80003DFFFF 3D00003D7FFF 3C80003CFFFF 3C00003C7FFF 3B80003BFFFF 3B00003B7FFF 3A80003AFFFF 3A00003A7FFF 39800039FFFF 390000397FFF 38800038FFFF 380000387FFF 37800037FFFF
FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF
3FF000-3FFFFF 3FE0003FEFFF 3FD0003FDFFF 3FC0003FCFFF 3FB0003FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E80003EFFFF 3E0000-3E7FFF 3D80003DFFFF 3D00003D7FFF 3C80003CFFFF 3C00003C7FFF 3B80003BFFFF 3B0000-3B7FFF
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 30.
16, 32, and 64 Mbit Memory Addressing (Sheet 2 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit 3A80003AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-Mbit 32-Mbit 64-Mbit 370000377FFF 36800036FFFF 360000367FFF 35800035FFFF 350000357FFF 34800034FFFF 340000347FFF 33800033FFFF 330000337FFF 32800032FFFF 320000327FFF 31800031FFFF 310000317FFF 30800030FFFF 300000307FFF 2F80002FFFFF 2F00002F7FFF 2E80002EFFFF 2E00002E7FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit 1A80001AFFFF 1A00001A7FFF 19800019FFFF 190000197FFF 18800018FFFF 180000187FFF 17800017FFFF 170000177FFF 16800016FFFF 160000167FFF 15800015FFFF 150000157FFF 14800014FFFF 140000147FFF 13800013FFFF 130000137FFF 12800012FFFF 120000127FFF 11800011FFFF
A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF
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Datasheet
C3 SCSP Flash Memory
Table 30.
16, 32, and 64 Mbit Memory Addressing (Sheet 3 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 This column continues on next page 16-Mbit 32-Mbit 64-Mbit 2D80002DFFFF 2D00002D7FFF 2C80002CFFFF 2C00002C7FFF 2B80002BFFFF 2B00002B7FFF 2A80002AFFFF 2A00002A7FFF 29800029FFFF 290000297FFF 28800028FFFF 280000287FFF 27800027FFFF 270000277FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit 110000117FFF 10800010FFFF 100000107FFF 0F80000FFFFF 0F00000F7FFF 0E80000EFFFF 0E00000E7FFF 0D80000DFFFF 0D00000D7FFF 0C80000CFFFF 0C00000C7FFF 0B80000BFFFF 0B00000B7FFF 0A80000AFFFF
10000-17FFF 08000-0FFFF 00000-07FFF
310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E80002EFFFF 2E0000-2E7FFF 2D80002DFFFF 2D00002D7FFF 2C80002CFFFF 2C00002C7FFF 2B80002BFFFF 2B0000-2B7FFF 2A80002AFFFF
This column continues on next page
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Table 31.
16, 32, and 64 Mbit Memory Addressing (Sheet 1 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 1F80001FFFFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 16-Mbit 32-Mbit 64-Mbit 26800026FFFF 260000267FFF 25800025FFFF 250000257FFF 24800024FFFF 240000247FFF 23800023FFFF 230000237FFF 22800022FFFF 220000227FFF 21800021FFFF 210000217FFF 20800020FFFF 200000207FFF 1F80001FFFFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit 0A00000A7FFF 09800009FFFF 090000097FFF 08800008FFFF 080000087FFF 07800007FFFF 070000077FFF 06800006FFFF 060000067FFF 05800005FFFF 050000057FFF 04800004FFFF 040000047FFF 03800003FFFF 030000037FFF 02800002FFFF 020000027FFF 01800001FFFF 010000017FFF
2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF
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Datasheet
C3 SCSP Flash Memory
Table 31.
16, 32, and 64 Mbit Memory Addressing (Sheet 2 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-Mbit 32-Mbit 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 19800019FFFF 190000197FFF 18800018FFFF 180000187FFF 17800017FFFF 170000177FFF 16800016FFFF 160000167FFF 15800015FFFF 150000157FFF 14800014FFFF 140000147FFF 64-Mbit 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 19800019FFFF 190000197FFF 18800018FFFF 180000187FFF 17800017FFFF 170000177FFF 16800016FFFF 160000167FFF 15800015FFFF 150000157FFF 14800014FFFF 140000147FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit 00800000FFFF 000000007FFF
208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E80001EFFFF 1E0000-1E7FFF 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B0000-1B7FFF 1A80001AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF
Datasheet
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Table 31.
16, 32, and 64 Mbit Memory Addressing (Sheet 3 of 3)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF 16-Mbit 32-Mbit 13800013FFFF 130000137FFF 12800012FFFF 120000127FFF 11800011FFFF 110000117FFF 10800010FFFF 100000107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000DFFFF D0000-D7FFF C8000CFFFF C0000-C7FFF 64-Mbit 13800013FFFF 130000137FFF 12800012FFFF 120000127FFF 11800011FFFF 110000117FFF 10800010FFFF 100000107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit
170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF This column continues on next page
This column continues on next page
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Datasheet
C3 SCSP Flash Memory
Table 32.
16, 32, and 64 Mbit Memory Addressing (Sheet 1 of 2)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit 0F0000-0F7FFF 0E80000EFFFF 0E0000-0E7FFF 0D80000DFFFF 0D00000D7FFF 0C80000CFFFF 0C00000C7FFF 0B80000BFFFF 0B0000-0B7FFF 0A80000AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 16-Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 32-Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 64-Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16-Mbit
32-Mbit
Datasheet
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C3 SCSP Flash Memory
Table 32.
16, 32, and 64 Mbit Memory Addressing (Sheet 2 of 2)
16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64-Mbit 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) 4 4 4 4 4 4 4 16-Mbit 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 32-Mbit 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 64-Mbit 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Size (KW) 32 32 32 32 32 32 32
16-Mbit
32-Mbit
Appendix D Device ID Table
Table 33. Device ID
Read Configuration Address and Data Item Manufacturer Code Device Code 16-Mbit x 16-T 16-Mbit x 16-B 32-Mbit x 16-T 32-Mbit x 16-B Note: x16 x16 x16 x16 00001 00001 00001 00001 88C2 88C3 88C4 88C5 x16 Address 00000 Data 0089
Other locations within the configuration address space are reserved by Intel for future use.
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Datasheet
C3 SCSP Flash Memory
Appendix E Protection Register Addressing
Table 34. Protection Register Addressing
Word-Wide Protection Register Addressing Word LOCK 0 1 2 3 4 5 6 7 Note: Use Both Factory Factory Factory Factory User User User User A7 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0
All address lines not specified in the above table must be 0 when accessing the Protection Register--for example, A21-A8 = 0.
Datasheet
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Appendix F Mechanical and Shipping Media Details
F.8 Mechanical Specification
A1 Index
1 A B C D E F G H 2 3 4 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1
S2 S1
A B C D E F G H
E
b
e D
Top View - Ball Down
A2 A
Bottom View - Ball Up
Y
A1
Note:
Shaded pins indicate upper address balls for 64-Mbit and 128-Mbit devices. In all Flash and SRAM combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated).
Table 35.
Packaging Specifications (0.18m and 0.25m) (Sheet 1 of 2)
Millimeters Sym Min Nom Max 1. 400 0.250 0.960 0.350 9.900 D 11.900 13.900 0.400 10.00 12.000 14.000 0.450 10.100 12.100 14.100 0.0138 0.3898 0.4685 0.5472 0.0098 0.0378 0.0157 0.3937 0.4724 0.5512 0.0177 0.3976 0.4764 0.5551 Min Inches Nom Max 0.0551
Package Height Ball Height Package Body Thickness Ball Lead Diameter Package Body Length - 16-Mbit/2-Mbit Package Body Length - 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Package Body Length - 32-Mbit/8-Mbit Package Body Width - 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit
A A1 A2 b
E
7.900
8.000
8.100
0.3110
0.3150
0.3189
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Datasheet
C3 SCSP Flash Memory
Table 35.
Packaging Specifications (0.18m and 0.25m) (Sheet 2 of 2)
Millimeters Sym Min Nom 0.800 66 0.100 Max Min Inches Nom 0.0315 66 0.0039 Max
Pitch Ball (Lead) Count Seating Plane Coplanarity
e N Y
Corner to Ball A1 Distance Along E
16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit Corner to Ball A1 Distance Along D 16-Mbit/2-Mbit Corner to Ball A1 Distance Along D 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Corner to Ball A1 Distance Along D 32-Mbit/8-Mbit S2 0.500 1.500 2.500 0.600 1.600 2.600 0.700 1.700 2.700 0.0197 0.0591 0.0984 0.0236 0.0630 0.1024 0.0276 0.0669 0.1063 S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Datasheet
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C3 SCSP Flash Memory
Table 36. Packaging Specifications (0.13m)
Millimeters Sym Package Height 16/02-Mb, 16/04-Mb, 32/08-Mb A Package Height 32/04-Mb Ball Height 16/02-Mb, 16/04-Mb, 32/08-Mb A1 Ball Height 32/04-Mb Package Body Thickness 16/02-Mb, 16/04-Mb, 32/08-Mb A2 Package Body Thickness 32/04-Mb Ball (Lead) Width 16/02-Mb, 16/04-Mb, 32/08-Mb b Ball (Lead) Width 32/04-Mb Package Body Length 16/02-Mb, 16/04-Mb D Package Body Length 32/04-Mb, 32/08-Mb Package Body Width 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Corner to Ball A1 Distance Along D 16/02-Mb, 16/04-Mb Corner to Ball A1 Distance Along D 32/04-Mb, 32/08-Mb E e N Y S1 S2 S2 1.100 0.500 1.500 1.200 0.600 1.600 11.900 7.900 12.000 8.000 0.800 66 0.100 1.300 0.700 1.700 0.0433 0.0197 0.0591 0.0472 0.0236 0.0630 12.100 8.100 0.4685 0.3110 0.4724 0.3150 0.0315 66 0.0039 0.0512 0.0276 0.0669 0.4764 0.3189 0.350 9.900 0.40 10.000 0.450 10.100 0.0138 0.3898 0.0157 0.3937 0.0177 0.3976 0.325 0.960 0.375 0.425 0.0128 0.0378 0.0148 0.0167 0.250 0.860 0.0098 0.0339 0.200 1. 400 0.0079 0.0551 Min Nom Max 1. 200 Min Inches Nom Max 0.0472
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Datasheet
C3 SCSP Flash Memory
F.9
Media Information
Device Pin 1
Tray Chamfer
Note:
Top view, ball side down. Drawing is not to scale and is only designed to show orientation of devices.
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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C3 SCSP Flash Memory
Figure 21.
SCSP Device in 24 mm Tape (10 mm x 8 mm and 12 mm x 8 mm)
Device Pin 1
Note:
Top view, ball side down.
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Datasheet
C3 SCSP Flash Memory
Appendix G Additional Information
Table 37. Related Documents
Order Number 292216 292215 Contact Your Intel Representative 297874 Document/Tool AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Flash Data Integrator (FDI) Software Developer's Kit FDI Interactive: Play with Intel's Flash Data Integrator on Your PC
Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools.
Datasheet
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Appendix H Ordering Information
.
Table 38.
Ordering Information for Product Combinations with 0.25 m to 0.13 m Flash
RD28F1602C3TD7 0
Package
RD = Leaded Ball Stacked -CSP PF = Lead-Free Ball Stacked-CSP
Access Speed (ns)
16 Mbit = 70, 90, or 110 ns 32 Mbit = 70 or 90 ns
Product Line Designator
28F or 38F = Intel Flash Memory
(R)
Technology Differentiator
Flash Density
320 = x16 (32 Mbit) 160 = x16 (16 Mbit)
D = 0.13m = 0.25m or 0.18m (refer to access speed for differientation)
Parameter Location
T = Top Blocking B = Bottom Blocking
SRAM Device Density
8 = x16 (8 Mbit) 4 = x16 (4 Mbit) 2 = x16 (2 Mbit)
Product Family
C = Advanced+ Boot Block Flash Memory
Table 39.
Ordering Information for Combinations specific to 32M 0.13 m Flash
RD38F1010C0ZTL0
Package
RD = Leaded Ball Stacked-CSP PF = Lead-Free Ball Stacked-CSP
Device Details
0 = Original Version of this product: Flash Speed = 70 ns Flash Process = 0.13 m Vccq = 2.7 V to 3.3 V
Product Line Designator
38F = Intel(R) Flash Stacked Memory
Density
Flash #1 = 1 = 32 Mbit Flash #2 = 0 = No Die Flash #3 = 1 = 4 Mbit SRAM = 2 = 8 Mbit SRAM Flash #4 = 0 = No Die
Pinout Indicator
L = 72 ball "I"-ballout
Parameter Location
T = Top Blocking B = Bottom Blocking
Product Family
C = Advanced+ Boot Block Flash Memory
Voltage
Z = 3.0 V I/O
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Datasheet
C3 SCSP Flash Memory
Table 40.
Ordering Information Valid Combinations
0.25m C3 SCSP 0.18m C3 SCSP RD28F3208C3T70 RD28F3208C3B70 32-Mbit No longer available. RD28F3208C3T90 RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70 RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 16-Mbit RD28F1604C3B110 RD28F1602C3T90 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110 RD28F1602C3T70 RD28F1602C3B70 PF28F1602C3TD70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70 0.13m C3 SCSP RD38F1010C0ZTL0 RD38F1010C0ZBL0 PF38F1010C0ZTL0 PF38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0
Datasheet
Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004
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